With the rapid development of semiconductor manufacturing technology, the semiconductor device is progressing towards higher component density and higher integration degree. With the increasing of the component density and the integration degree of the semiconductor device, gate dimensions of planar transistor are scaled down, reducing effective length of the gate. As such, the ratio of charges in the depletion layer actually controlled by the gate voltage decreases, and the control capability of the gate-to-channel current becomes weak, leading to a short-channel effect and causing a leakage current issue, thus affecting the electrical properties of the semiconductor device.
A fin field effect transistor (FET) formed on a silicon-on-insulator (SOI) substrate can decrease the parasitic capacitance and reduce the leakage current. However, the FinFET formed on the SOI substrate has a disadvantage of high manufacturing cost. The FinFET formed on a bulk silicon substrate (bulk-FinFET) has many advantages, such as low cost, desired heat dissipation performance, and compatible with planar transistor device. However, the bulk-FinFET has a disadvantage of the large leakage current. The disclosed semiconductor structures and methods are directed to solve one or more problems set forth above and other problems.